Responsibilities: Develop and test RTL modules on AMD/Xilinx FPGA devices (required) and ASIC targets (preferred).Develop and maintain build/simulation scripts.Write test cases using Python to validate our design.Create software interfaces from our FPGA-based systems to Windows and Linux systems software at the HAL layer.Collaborate in a team environment across multiple engineering disciplines and with researchers.Minimum Skills: 5+ years of FPGA design experience using Verilog, SYSTEMVERILOG5+