Austin, Texas
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Today
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Required experience Good knowledge of SV/UVM.Good knwledge of verilog/vhdl/C/C++Experience in any scripting language Perl/Python/shell.Knowledge of AMBA
Full-time