We are looking for an experienced DFT Engineer to join an ASIC Design Team on a 1-year contract. You will be responsible for ensuring testability throughout the ASIC design process while collaborating with cross-functional teams. Responsibilities: Lead DFT efforts in ASIC designs using VHDL, Verilog, or System Verilog. Follow company ASIC development process and implement DFT methodologies. Work with Cadence/ Mentor ATPG tools, hierarchical scan testing, JTAG, and memory/logic BIST. Collaborate