Role: Silicon Design Engineer Location: Boxborough MA 01719 | Hybrid Duration: 12+ months The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and implementing DDR IPs. The focus of the activity will be centered around spice simulations and behavior modeling. The supporting team is an established group of talented Analog/Mixed-Signal integrated circuit designers. The site includes the direct supervisor, AMS manager, IP director, and majority of the AMS