Search Jobs | Dice.com

San Jose, California

•

Today

Position: SDC Engineer (eInfochips Inc) Job Description: Position: SDC Engineer (eInfochips Inc) Location: San Jose CA (Day-1 Onsite) What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC chang

Full-time

Design Implementation Engineer- Graphics

San Diego, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics team, the successful applicant will help integrate, implement and deliver state of the art GPU cores and will be working closely with the graphics microarchit

Full-time

USD 161,800.00 - 242,600.00 per year

Applications Engineering, Sr Staff Engineer - 10787

Sunnyvale, California

•

Today

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly

Full-time

ASIC Engineering Technical Leader - SDC

San Jose, California

•

Today

The application window is expected to close on: July 31, 2025. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role requires being onsite in San Jose, CA 4+ days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-

Full-time

Hardware Design Engineering Intern/ Co-Op (Graduate | Fall 2025 | Hybrid)

Remote or Austin, Texas

•

Today

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellen

Full-time

USD 99,840.00 per year

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal)

Huntington Beach, California

•

Today

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Huntington Beach or El Segundo, CA. From complex digitally beamformed phased arrays for constellation satellite prog

Full-time

USD 126,650.00 - 171,350.00 per year

STA Engineer/SDC Engineer

San Jose, California

•

7d ago

About the Role:Seeking an experienced STA/SDC engineer to own block and full-chip constraints, perform Static Timing Analysis (PrimeTime/Tempus), and collaborate with design and physical design teams for timing closure. Key Skills: Strong expertise in STA and SDC constraints (functional & test modes) Experience with PrimeTime, Tempus, and synthesis tools (Synopsys DC/DCG/FC) Verilog/SystemVerilog design knowledge CDC/glitch analysis (Spyglass CDC), Formal Verification (Formality, LEC) Scripting

Easy Apply

Contract

$60 - $70

STAEngineer

San Jose, California

•

Today

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficien

Easy Apply

Contract

Filter Results

Job post features

Posted date

Work settings

Employment type

Employer type

Work authorization