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Mountain View, California

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7d ago

A client of Innova Solutions is immediately hiring for a Design Verification Engineer Position type: Contract Location: Mountain View, CA-Onsite As a Design Verification Engineer, you will be responsible for: Job description: Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirements.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC leve

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Contract

$60 - $70

Design Verification Engineer - SOC

San Jose, California

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12d ago

Millennium Software & Staffing is looking for Design Verification Engineer SOC at San Jose, CA Below are the details: Title : Design Verification Engineer SOC Location : San Jose, CA TOP SKILLS: SOCUVM, System VerilogIntegrate GPU, CPU, Arm Based SystemPCIe, DDR, Ethernet, Bus ProtocolsPython Scripting Candidate should have average or above average Python SkillsExperience: 8+ years of experience in SOC, SystemVerilog/UVM methodologyExperience in EDA tools and scripting (Python, TCL, Perl, Shell

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Contract

Depends on Experience

Principal Design Verification Engineer

Hybrid in San Jose, California

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5d ago

Principal Design Verification Engineer A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security. As a Principal Design Verification Engineer, you ll play a critical role in the development of MIC

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Full-time

$160,000 - $180,000

Design Verification Engineer

San Jose, California

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Yesterday

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

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Full-time

Depends on Experience

AI HW Design Verification Engineer

Remote or Santa Clara, California

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Today

AI HW Design Verification Engineer Looking for a Senior Design Verification Engineer. This person will play a key role in quality and reliability of digital designs through comprehensive verification methodologies. This person should have a strong background in verification techniques/processes, problem solving skills, and skilled at delivering high quality designs. Scope: Develop & execute comprehensive verification strategies in order to validate complex digital designs, ensuring compliance w

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Full-time

USD70 - USD90 per hour, Benefits: 70-90/hr

Senior Design Verification Engineer - Ethernet PHY/PCS

Santa Clara, California

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2d ago

Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS Location: Santa Clara, CA Job Type: Contract, Full-time Experience: 7+ years We're seeking an experienced Senior Design Verification Engineer with expertise in Ethernet PHY or PCS to join our team in Santa Clara, CA. Responsibilities: - Develop and execute verification plans for Ethernet PHY or PCS - Create and maintain testbenches and test suites - Collaborate with design engineers to resolve verification issues - Strong understa

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Contract, Third Party

$180,000 - $200,000

Senior Design Verification Engineer, HW Compute Group

Sunnyvale, California

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Today

Job DescriptionAs a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interac

Full-time

Compensation information provided in the description

Mixed-Signal Design Verification Engineer

San Jose, California

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Today

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

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Contract, Third Party

$50 to 65 per hour

Digital SoC Design Verification Principal Engineer/Manager

Hybrid in San Jose, California

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12d ago

Digital SoC Design Verification Principal Engineer/Manager 140-225K (+ Pre-IPO Stock Options) San Jose, CA (hybrid 1 day/week remote, 4 days/week onsite) We are looking for an experienced Digital SoC Design Verification Principal Engineer/Manager to lead a team of engineers in developing innovative Open RAN SoC functional blocks for 5G cellular base stations. In this role, you will be responsible for driving the development of high-quality digital solutions and contributing to product definition

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Full-time

$140,000 - $220,000

Design Verification Engineer

Hybrid in San Jose, California

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Today

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci

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Full-time

$140,000 - $240,000

Satellite or Space FPGA Design / Verification Engineer

Remote

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6d ago

Job Title: Satellite or Space FPGA Design / Verification Engineer Duration: up to 3 months contract with possible extension Location: Remote Work / Work from Home Work Schedule: 5/40-1st Shift Pay Rate: $87.19/hr on W2 [the pay rate may differ depending on your skills, education, experience, and other qualifications] Featured Benefits: Medical Insurance in compliance with the ACA401(k)Sick leave in compliance with applicable state, federal, and local laws Job Description: ASIC/FPGA Engineer an

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Contract

$87.19

Staff Engineer, CPU Design Verification

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 157,000.00 - 243,000.00 per year

System Verilog UVM Design Verification Test Engineer

Remote

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27d ago

Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM/python test development for driving VIPs and other stimulus driversGeneration of test components such as monitors, scoreboards and python modelsCoverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies

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Contract

Up to $110

Design Verification

San Jose, California

•

Yesterday

Xpeerant prides itself in assisting our customers to achieve Market Window success by identifying and placing critical resource requirements. Securing the right talent is the most critical component of any project and directly relates to the success of any business. Market opportunities wait for no one. Finding the ideal fit is what Xpeerant has done for the last 26 years! We have a DV contract located in San Jose, CA. Someone with good design and verification experiences on protocol and proce

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Contract

Depends on Experience

Mechanical Engineer (kinematic design, optics, precision mechanical design) in Santa Clara, CA

Santa Clara, California

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5d ago

Mechanical Engineer (kinematic design, optics, precision mechanical design) in Santa Clara, CA 7+ to 10 years of experience POSITION: Mechanical Engineer (kinematic design, optics, precision mechanical design) LOCATION: Santa Clara, CA (onsite) DURATION: Full-Time SALARY: Excellent Compensation with benefits TRAVEL: Occasional SKILLS: Mechanical Engineer, kinematic design, optics, precision mechanical design principles DESCRIPTION: This position is in the Semiconductor Infrastructure Solution

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Full-time

Depends on Experience

Sr. Package Design Engineer ASIC/SOC

Hybrid in San Jose, California

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2d ago

Job Title Sr. Package Design Engineer ASIC/SOC Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available The Role: Sr. Package Design Engineer We are seeking a highly experienced Package Design Engineer with 7+ years of hands-on

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Full-time

Depends on Experience

Physical Design Engineer Custom ASIC / SoC

Hybrid in San Jose, California

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2d ago

Job Title: Physical Design Engineer Custom ASIC / SoC Hybrid San Jose, CA Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available Position Overview Physical Design Engineer: We are seeking a hands-on Physical Design Engineer w

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Full-time

Depends on Experience

Product Design Engineer V

Cupertino, California

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Today

Job Title: Product Design Engineer Job Location: Cupertino, CA Work Model: 3-days onsite and 2 days WFH Job Duration: 06+ month contract with possibility of extension Max Hourly Rate($): $110-115/hour on W2 + Benefits Key Qualifications: High degree of motivation, curiosity, passion and creativity Design intelligence: mechanical intuition, creative problem solving, spatial reasoning, attention to detail Engineering fundamentals: statics, strength of materials, material science, statistics Excell

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Contract

BASED ON EXPERIENCE

ASIC Verification Engineer

San Jose, California

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Today

The application window is expected to close on 7/30/25. This role will work onsite out of our San Jose, CA office. Who We Are: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon arc

Full-time

Studio Engineer - Industrial Design Support

Remote or Mountain View, California

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Today

Studio Engineer Industrial Design Support Location: Mountain View, CA On-site support required Tuesdays & Wednesdays WFH optional for remaining weekdays. (Schedule subject to change at the discretion of the host team). Scope: The vendor will provide studio engineering expertise in support of industrial design for production programs and exploratory concept development related to: Vehicle interiors Vehicle exteriors Autonomous sensing systems Integration of sensor pods into vehicle designs T

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Full-time

USD50 - USD60 per hour

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