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Design For Test (DFT) Engineer

NUBYT, INC.

San Jose, California • 8d ago

Easy Apply

Contract

100 - 130

Job Details

Skills

DFT
ATPG
Python
Static Timing Analysis
BIST
Tessent Flow
VTRAN
PrimeTime

Summary

Role: Design For Test (DFT) Engineer

Location: San Jose, CA (Onsite: M-F)

Duration: 6 Months Contract

Pay Rate: $100-130/hr W2

Description:

Looking for a Design-for-Test contractor to test and validate the next generation chips.
Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.

Job Responsibilities:

Experience with memory BIST – Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting – Tcl/Perl/Python
Experience with scan compression – SEQ/Ultra/TestKompress
Experience with ATPG – Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation – VTRAN
Experience with RTL design – Verilog/system Verilog
Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)

Required Skills and Experience:

5+ years relevant industrial DFT experience
Excellent problem solving and debugging skills
Ability to complete assignments independently

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91117675
Position Id: 9075961
Posted 30+ days ago

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Ganesh Iyer

Recruiter @ NUBYT, INC.

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Job Details

Skills

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Static Timing Analysis
BIST
Tessent Flow
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PrimeTime

Summary

Role: Design For Test (DFT) Engineer

Location: San Jose, CA (Onsite: M-F)

Duration: 6 Months Contract

Pay Rate: $100-130/hr W2

Description:

Looking for a Design-for-Test contractor to test and validate the next generation chips.
Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.

Job Responsibilities:

Experience with memory BIST – Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting – Tcl/Perl/Python
Experience with scan compression – SEQ/Ultra/TestKompress
Experience with ATPG – Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation – VTRAN
Experience with RTL design – Verilog/system Verilog
Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)

Required Skills and Experience: