Verification Engineer Jobs

1 - 20 of 65 Jobs

Senior Anti - Tamper Verification Engineer -Job Title - Senior Anti - Tamper Verification Engineer -

HII Mission TechnologiesCompany Name - HII Mission Technologies

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Dayton, Ohio, USA

Full-time

Requisition Number: 19084 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Hours Per Week: 40 Security Clearance: Secret Level of Experience: Senior Job Description Interact with USG program offices and weapon and sensor system manufacturers in technical interchange meetings and Program reviews to achieve a technically acceptable Anti-Tamper implementation. Analyze and conduct vulnerability analysis of system level implementations and architectures, and review Anti-Tamper pl

Principal Design Verification EngineerJob Title - Principal Design Verification Engineer

Microsoft CorporationCompany Name - Microsoft Corporation

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Mountain View, California, USA

Full-time

$desc Qualifications Required Qualifications: 9+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, C

Design Verification Engineer at San Jose CAJob Title - Design Verification Engineer at San Jose CA

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Role: Design Verification Engineer Location: San Jose CA Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA pro

Senior Verification EngineerJob Title - Senior Verification Engineer

Microsoft CorporationCompany Name - Microsoft Corporation

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Redmond, Washington, USA

Full-time

$desc Qualifications Required Qualifications: 7+ years of technical engineering experience in hardware design verification, verification methodologies, and system Verilog OR Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 5+ years of technical engineering experience OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 3+ years of techn

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

Microsoft CorporationCompany Name - Microsoft Corporation

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Mountain View, California, USA

Full-time

$desc Qualifications Required/Minimum Qualifications: 7+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Enginee

Verification EngineerJob Title - Verification Engineer

JobotCompany Name - Jobot

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San Jose, California, USA

Full-time

Come deliver innovative solutions that exceed expectations every time with an amazing company! This Jobot Job is hosted by: Samantha Cunningham Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $125,000 - $175,000 per year A bit about us: Our Client is an IT Company, that enables digital transformation for enterprises and technology providers by delivering seamless customer experiences, business efficiency, and actionable insights. Our Client

Verification Engineer - Validation, Networking, Python @ Hillsboro, ORJob Title - Verification Engineer - Validation, Networking, Python @ Hillsboro, OR

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Hillsboro, Oregon, USA

Contract

We have an immediate opportunity with one of our direct clients. Please find the job description below and if you are interested, please forward your resume and share below details. Best contact number: Work Authorization: Hourly Payrate expected (W2): Month & Day of birth: Present Location & Zip-code: Job Title: Verification Engineer Duration: 9 Months Contract Location: Hillsboro, OR Hybrid: Must work 2-3 days between Tuesday - Thursday Onsite Min education requirement: Bachelor's de

Formal Verification EngineerJob Title - Formal Verification Engineer

Technical LinkCompany Name - Technical Link

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Toronto, Ontario, Canada

Full-time

Description : This position is for a Formal Design Verification Engineer. The successful candidate will use formal verification technologies to perform functional verification of design blocks inside Custom AI IPs. Formal technologies include Formal Property Verification, Sequential Equivalence Checking and Data path Validation Responsibilities : Creating and executing verification plan Writing formal properties or formal testbench Running formal verification tools Debugging failures Discussing

Verification EngineerJob Title - Verification Engineer

HR PunditsCompany Name - HR Pundits

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Lisle, Illinois, USA

Full-time

Required Qualification: 5+ years of experience in embedded development testing and/or test automation.3+ years of experience with unit testing tools preferably Vector-CAST, QAC, etc.1+ years of experience in Static Analysis (e.g., PC lint)2+ years of team lead experienceExperience in requirements-based testing for automotive domain.Experience in software development life cycle, coding standards, code reviews, configuration management, build processes, and CICD.Experience in developing test scrip

Hardware Verification Engineer - VHDLJob Title - Hardware Verification Engineer - VHDL

Indotronix International CorpCompany Name - Indotronix International Corp

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Azusa, California, USA

Contract

Onsite Job: Hardware Verification Engineer - VHDL Location: Azusa, CA 91702 Duration: 06+ Months Contract Work Schedule: 9/80 Bachelor's degree with 6+ years' experience. Active Secret Clearance - Required Job Description: Conducts research, design, development, and testing of information processing hardware such as computer chips, circuit boards, computer systems, and electrical components.Designs new or modifies existing products, develops technical specifications for production, analyzes har

Design Verification EngineerJob Title - Design Verification Engineer

LTIMindtreeCompany Name - LTIMindtree

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Mountain View, California, USA

Full-time

About Us LTIMindtree is a global technology consulting and digital solutions company that enables enterprises across industries to reimagine business models, accelerate innovation, and maximize growth by harnessing digital technologies. As a digital transformation partner to more than 700+ clients, LTIMindtree brings extensive domain and technology expertise to help drive superior competitive differentiation, customer experiences, and business outcomes in a converging world. Powered by nearly 90

Verification EngineerJob Title - Verification Engineer

Happiest Minds Technologies LimitedCompany Name - Happiest Minds Technologies Limited

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Fremont, California, USA

Third Party, Contract

Verification Engineer Fremont, CA BSEE or BSCS, or equivalent 5+ years of ASIC/FPGA verification experience using SystemVerilog / UVMMust have experience with:Verification flow using Questa simulationDeveloping verification plansDesigning and implementing SystemVerilog / UVM test benches for constrained-random verificationDeveloping functional coverage modelsWriting and debugging directed and random test casesExperience with automation/scripting (Python, Perl, sed, awk, tcl/tk, sh)Experience wit

Sr. Staff Systems Verification EngineerJob Title - Sr. Staff Systems Verification Engineer

Abbott LaboratoriesCompany Name - Abbott Laboratories

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Pleasanton, California, USA

Full-time

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 114,000 colleagues serve people in more than 160 countries. Working at Abbott At Abbott, you can do work that matters, grow, and learn, care for yourself and family, be your true self and live a full life. Yo

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

Capgemini EngineeringCompany Name - Capgemini Engineering

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Austin, Texas, USA

Full-time

Senior Design Verification Engineer Austin TX (Hybrid role) Life at Capgemini Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer: Flexible work Healthcare including dental, vision, mental health, and well-being programsFinancial well-being programs such as 401(k) and Employee Share Ownership PlanPaid time off and paid holidays Paid parental leaveFamily building benefits like adoption assistance, surrogacy,

Design Verification EngineerJob Title - Design Verification Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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Austin, Texas, USA

Contract

Job Title: Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean re

FPGA Design Verification EngineerJob Title - FPGA Design Verification Engineer

General Dynamics CorporationCompany Name - General Dynamics Corporation

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Dedham, Massachusetts, USA

Full-time

Responsibilities for this Position FPGA Design Verification Engineer ID: 2024-63075 USA-MA-Dedham Required Clearance: Secret Posted Date: 5/1/2024 Category: Engineering-Hardware Employment Type: Full Time Hiring Company: General Dynamics Mission Systems, Inc. Basic Qualifications Requires a Bachelors degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of

Design Verification EngineerJob Title - Design Verification Engineer

West Coast Consulting LLCCompany Name - West Coast Consulting LLC

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SARC GPU

Contract

Job Description Vertical Technical As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities: Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification. Review Architecture and Micro

ASIC & FPGA Verification EngineerJob Title - ASIC & FPGA Verification Engineer

GeoLogics CorporationCompany Name - GeoLogics Corporation

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Littleton, Colorado, USA

Contract

Role: ASIC & FPGA Verification Engineer Client: DOD-Aerospace Location: Littleton, CO (Hybrid) Duration: 6-month contract Hourly Rate: up to $120/hr (W2, non-benefited) Position Description: Work with low SWaP, radiation hardened, space rated devices.Devise a unique verification plan for a given design.Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.Develop requirements, test cases, build test benches, ge

Design Verification Engineer with UVM,OVM, SystemVerilog & PythonJob Title - Design Verification Engineer with UVM,OVM, SystemVerilog & Python

PDDN IncCompany Name - PDDN Inc

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Santa Clara, California, USA

Contract, Third Party

Role: Design Verification Engineer Location: Santa Clara, CA Interview: Phone/Skype Job Type: Contract Background check: Mandatory Meet and great: Mandatory UVM/OVM/SystemVerilog/Python/C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Creat

Sr. Software System Verification EngineerJob Title - Sr. Software System Verification Engineer

Abbott LaboratoriesCompany Name - Abbott Laboratories

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Burlington, Massachusetts, USA

Full-time

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 114,000 colleagues serve people in more than 160 countries. WORKING AT ABBOTT At Abbott, You Can Do Work That Matters, Grow, And Learn, Care For Yourself And Family, Be Your True Self And Live a Full Life. You'