Graphics GPU RTL Design Engineer Jobs in Los Angeles, CA

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Embedded Linux Senior Software Engineer - Optimisation

Canonical - Jobs

Remote or Chicago, Illinois, USA

Full-time

Job DescriptionJob DescriptionWork across the full Linux stack from kernel through GUI to optimise Ubuntu, the world's most widely used Linux desktop and server, for the latest silicon. The role is a fast-paced, problem-solving role that's challenging yet very exciting. The right candidate must be resourceful, articulate, and able to deliver on a wide variety of solutions across PC and IoT technologies. Our teams partner with specialist engineers from major silicon companies to integrate next-ge

AIOps SYSTEMS ARCHITECT- REMOTE - FED GOV

ASD, Inc.

Remote

Contract

As a System Engineer Expert, you will support the business strategy that helps ensure today is safe and tomorrow is smarter. Our work depends on System Architect joining our team to enhance our tailored offerings for customer environments and provide interesting and compelling work for our employees. Use Java, PHP, Python and/or COTS automation tools to ensure the integration and presentation of data through dashboards that meet customer requirementsDocument Linux appliance build and configurati

ASIC Verification Engineer

Q1 Technologies, Inc.

Remote or Santa Clarita, California, USA

Full-time, Third Party, Contract

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units

Senior ASIC / FPGA Design Verification Engineer

Technical Link

Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing