ASIC RTL DESIGN ENGINEER

Overview

On Site
Depends on Experience
Contract - W2
Contract - Independent
Contract - 12 Month(s)

Skills

ARM
AXI
EDA
Python
Tcl
Verilog
Veritas Cluster Server
Intellectual Property

Job Details

Location - Bay Area or San Deigo

Type - Contract

7+ years of related technical engineering experience

5+ years of experience applying digital design principles in SoC and/or IP development.

Proficient in Verilog/System Verilog coding constructs.

Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)

Experience with high speed PCIe designs and protocols.

Experience with Industry standard interface protocols such as AXI, APB, etc.

Experience with ARM Fabric IPs.

Experience with IPXACT.

Understanding of Computer Architecture fundamentals.

Ability to write scripts using Python, Tcl, Perl etc.

Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.

Proficiency with UPF (Low power intent)

Proficiency in clock crossing techniques.

Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

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