IC ASIC RTL Design Engineer

Summary

Join an ambitious and highly experienced team of silicon and distributed systems experts as a RTL design engineer. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers.

We are looking for talented, motivated engineers with experience in building large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced designers who have the range to contribute across the full lifecycle of complex chip development, and who enthusiastically seek full ownership of large scale, challenging designs from concept to production.

Roles and Responsibilities

• Ownership of all aspects of the design process, from analysis of the design approach and tradeoffs, to specification, through RTL implementation.
• Delivery of a robust, high performance design that meets the timing, area, reliability, testability, and power requirements set by the cross-functional engineering team.
• Work with system software, architecture, and microarchitecture experts on the functional and performance requirements in the development of novel, high throughput engines for processing, moving, storing, and scheduling of data.
• Support functional verification, from the involvement in setting the verification strategy, to the development of the test plan, through the execution of the testing and coverage phases.
• Support for performance validation, to ensure that the product meets the strenuous performance demands of modern data centers across diverse use cases.
• Support silicon bringup and post-silicon testing of mission critical functions.

Skills/Qualifications

Proven industry experience and successful track record in designing and building one or more of the following, in advanced silicon geometries:

• High-performance interface logic and/or processing pipelines for any popular bus or networking protocol such as PCIe, CXL, NV-Link, Ethernet, Infiniband, etc.
  • Experience with PCIe Gen5/6 and CXL at the Transaction Layer is preferred.
• High-performance pipelines with multi-threaded datapaths and ordering capabilities. Demonstrating expert capability in designing blocks such as DMA controllers and queueing/doorbell engines;

Expert knowledge of SystemVerilog

Good knowledge of Python, Perl, or other scripting languages

Junior role: Minimum BSEE/CE + 3 years or MSEE/CE + 2 years experience

Mid role: Minimum BSEE/CE + 7 years or MSEE/CE + 5 years experience

About Us
Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.

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