ASIC Design Verification

Overview

$90
Accepts corp to corp applications
Contract - 12+

Skills

ASIC
Design

Job Details

Role : ASIC Verification Engg

Location : Remote

Job Description:

  • Writing directed and random test cases, debugging failures, filing, and closing bugs
  • Writing, analyzing and achieving coverage metrics
  • Identify issue and co-fix it with design engineer
  • Create and execute test plans and test cases to verify that products meet product requirements and customer expectations
  • Create and execute targeted engineering evaluations at the request of the design engineering staff
  • Develop test plans and test bench
  • Should have experience in any of below-
  1. Core Sight Debug
  2. System Scenarios/stress (arm architecture knowledge)
  3. Performance/Power use cases
  4. Low Power Aware
  5. GLS
  6. DFT
  7. Production Die Level Functional Testing

Role : Physical Design Engg

Job Description :

  • Develop a variety of advanced high-performance interface IPs, test chips and subsystems (e.g. Serdes/DDR/HDMI/MIPI/USB etc.)
  • Create physical design methodologies and automation scripts for various implementation steps by leveraging Synopsys EDA ecosystem.
  • Ensure timely incoming and outgoing deliveries, report on project progress, interact and collaborate with multiple cross functional teams and the product team, and provide technical support to customers when needed.

Skills Needed

  • A relevant degree in Electrical or Computer Engineering, or Computer Science.
  • 5+ years of hands-on experience in ASIC physical implementation and EDA tools.
  • Solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design
  • Should have strong experience in Timing Constraints and Synthesis .
  • Knowledge of industry standard data file formats: Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPM, CMM.

Role: ASIC Design Engg

Location : Remote

Skills Needed:

  • Strong experience of ASIC Digital Design, front end experience.
  • Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
  • Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams
  • Should have experience in any of these
  1. Power / UPF / formal Structural Checks (VCLP)
  2. Lint / CDC / RDC
  3. FEV/LEC
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