Senior Packaging Design Engineer for Chip Design Company

Overview

Remote
$140,000 - $212,600
Full Time

Skills

Allegro
AutoCAD
Cadence
Collaboration
Communication
Continuous Improvement
Design Review
Feasibility Study
IP
Integrated Circuit
Intellectual Property
JEDEC
Layout
Management
Manufacturing
Mechanical Engineering
Multitasking
Packaging Design
Packaging Engineering
Routing
Workflow

Job Details

Job Title: Senior Packaging Design Engineer for Chip Design Company
Summary:
A premier chip and silicon IP provider making data faster and safer, is looking for a Packaging Design Engineer to join our Package Engineering team. This full-time role offers the opportunity to work on advanced packaging solutions with a world-class engineering team.
You ll lead chip-package co-design and manage layout development from concept through tape-out, focusing on yield, reliability, and manufacturability. Responsibilities include defining bump and ball maps, designing various package types (FCCSP, FCBGA, FCQFN, WLCSP, QFN), and working closely with cross-functional teams including Chip Design and SI/PI. This role also involves collaboration with OSATs and suppliers on design reviews, supporting simulation model creation, and driving continuous improvement in package design workflows and standards.
Responsibilities:

  • Drive early chip-package co-design and development of bump and ball map.
  • Own layout of package types such as FCCSP, FCBGA, FCQFN, WLCSP, QFN.
  • Collaborate with multiple cross-functional teams (Chip Design, SI/PI, Packaging)
  • Analyze cost/performance/reliability trade-offs to complete layout of new products and test chips.
  • Interact with OSAT partners and substrate/leadframe suppliers for design reviews and execution.
  • Continuous improvement of package design workflow and unified package design guidelines.
  • Assist with model creation for thermo-mechanical package simulations.

Requirements:

  • Proficiency with Cadence Allegro Package Designer (APD) and AutoCAD.
  • Minimum 4+ years of experience in packaging design and layout, preferably in an advanced silicon node.
  • Proven track record with multiple packaging types where products have gone to volume production.
  • Experience routing high-speed, high pin count devices and understanding of signal and power integrity fundamentals.
  • Knowledge of organic laminate substrate technologies and manufacturing capabilities.
  • Awareness of JEDEC standards and other specifications that may govern package design.
  • Understanding of package material properties related to high-volume production and reliability: temperature cycling, HAST, shock, vibration, thermal resistance, outgassing, etc.
  • Experience engaging with suppliers and OSAT factories to conduct manufacturing feasibility studies and ensure design readiness for production.
  • Excellent communication, initiative, multi-tasking, and time management.
  • Strong commitment and ability to work in cross functional and globally dispersed teams.

Location: San Jose, CA or Austin, TX (Remote or Hybrid arrangements available)
Type: Fulltime
Salary Range: $140,000-212,600 (DOE)

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

About OSI Engineering, Inc.