Overview
On Site
$70 - $80
Contract - Independent
Contract - W2
Contract - 12 Month(s)
Skills
Semiconductor background is a must
The focus is on System Verilog and UVM expertise
Job Details
Method Hub is Looking for Pre-Silicon Verification Engineer
Minimum Requirements
- Ideal range is 10-15 years: However, they are open to candidates with 7-20 years of experience
- Semiconductor background is a must
- Experience in the semiconductor industry is essential.
- The focus is on System Verilog and UVM expertise
- Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology
- Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
- Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
Preferred Qualifications
- Experience in the development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
- Experience with revision control systems like Mercurial(Hg), Git or SVN
- Experience with verification of ARM/RISC-V based sub-systems or SoCs
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