Overview
On Site
$70 - $80
Contract - W2
Skills
Design Verification Engineer
UVM
SoC AND AXI
AHB OR APB AND Python
Job Details
Role: Design Verification Engineer
Work Location: San Francisco, CA - Santa Clara, CA
Minimum Qualifications:
Proven track record of 'first-pass success' in ASIC development cycles.
Bachelor's degree in Computer Science, Computer Engineering, or a related technical field
8 to 10 years of hands-on experience with SystemVerilog/UVM methodology/Assertions/functional coverage
Experience in ARM Based SoC verification
Experience with AXI/AHB/APB
Proficiency with EDA tools and scripting languages (Python or TCL or Perl or Shell)
Knowledge of C or C++
Responsibilities:
Work on subsystems with multiple processors (ARM/RISC) and NOC, focusing on integration testing, and top-level functionalities.
Utilize your experience with UVM-based SoC verification.
Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
Engage in design verification involving concurrency and simultaneous memory access.
Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
Develop functional tests based on the verification test plan.
Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
? Utilize your experience with UVM-based SoC verification.
Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
Engage in design verification involving concurrency and simultaneous memory access.
Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
Develop functional tests based on the verification test plan.
Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
Work Location: San Francisco, CA - Santa Clara, CA
Minimum Qualifications:
Proven track record of 'first-pass success' in ASIC development cycles.
Bachelor's degree in Computer Science, Computer Engineering, or a related technical field
8 to 10 years of hands-on experience with SystemVerilog/UVM methodology/Assertions/functional coverage
Experience in ARM Based SoC verification
Experience with AXI/AHB/APB
Proficiency with EDA tools and scripting languages (Python or TCL or Perl or Shell)
Knowledge of C or C++
Responsibilities:
Work on subsystems with multiple processors (ARM/RISC) and NOC, focusing on integration testing, and top-level functionalities.
Utilize your experience with UVM-based SoC verification.
Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
Engage in design verification involving concurrency and simultaneous memory access.
Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
Develop functional tests based on the verification test plan.
Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
? Utilize your experience with UVM-based SoC verification.
Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
Engage in design verification involving concurrency and simultaneous memory access.
Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
Develop functional tests based on the verification test plan.
Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
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