Overview
On Site
USD 165,500.00 - 293,800.00 per year
Full Time
Skills
Integrated circuit
iPhone
iPad
FOCUS
SERDES
Data
Sensors
Intellectual property
IP
System on a chip
Collaboration
Leadership
Analog circuits
Specification
Mixed-signal integrated circuit
Design
CMOS
iOS development
ESD
Design for manufacturability
Circuit design
Problem solving
Planning
Layout
Assembly
Investor relations
International relations
Information retrieval
Migration
LVS
Cadence Virtuoso
Software development
Scripting
Perl
Tcl
Shell
Python
Communication
Cadence
Machine Learning (ML)
Artificial intelligence
Payments
Job Details
Summary
Posted: Oct 16, 2024
Weekly Hours: 40
Role Number:200573956
Apple Silicon Engineering Group (SEG) is seeking Analog Layout Leads to work on the next generation of Apple's systems-on-chip (SOCs)! These SOCs, with multi-billion transistors, serve as the core of iPhones and iPads. We focus on Analog/Mixed-Signal (AMS) circuits, including SerDes for data communication, PLLs for clock generation, and sensors for measuring all sorts of physical quantities.Analog Layout Engineers are essential in transforming design ideas into silicon, collaborating with circuit designers, and using sophisticated tools and methodologies. The work we do involves crafting custom analog designs to optimize the performance of our world-class products. This fast-paced work environment has endless learning opportunities and collaboration across dedicated multidisciplinary teams.Are you a self-motivated engineer passionate about working with ground breaking technology? If you want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products, this could be the role for you! The roles include crafting upcoming products, challenging oneself, and broadening skills in a dynamic, innovative work culture.
Description
Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop world-leading SOCs. As a part of the AMS layout team you will be delivering fully-verified, layout. This includes the following: Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floorplans and intricate circuits. Running complete sets of design verification tools available on AMS blocks. Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.
Minimum Qualifications
Key Qualifications
Preferred Qualifications
Education & Experience
Additional Requirements
Pay & Benefits
Posted: Oct 16, 2024
Weekly Hours: 40
Role Number:200573956
Apple Silicon Engineering Group (SEG) is seeking Analog Layout Leads to work on the next generation of Apple's systems-on-chip (SOCs)! These SOCs, with multi-billion transistors, serve as the core of iPhones and iPads. We focus on Analog/Mixed-Signal (AMS) circuits, including SerDes for data communication, PLLs for clock generation, and sensors for measuring all sorts of physical quantities.Analog Layout Engineers are essential in transforming design ideas into silicon, collaborating with circuit designers, and using sophisticated tools and methodologies. The work we do involves crafting custom analog designs to optimize the performance of our world-class products. This fast-paced work environment has endless learning opportunities and collaboration across dedicated multidisciplinary teams.Are you a self-motivated engineer passionate about working with ground breaking technology? If you want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products, this could be the role for you! The roles include crafting upcoming products, challenging oneself, and broadening skills in a dynamic, innovative work culture.
Description
Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop world-leading SOCs. As a part of the AMS layout team you will be delivering fully-verified, layout. This includes the following: Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floorplans and intricate circuits. Running complete sets of design verification tools available on AMS blocks. Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.
Minimum Qualifications
- B.S. and a minimum of 10 years relevant industry experience
Key Qualifications
Preferred Qualifications
- 10+ years in analog/mixed-signal layout design of deep submicron CMOS circuits, with at least 3+ years in FinFET technologies.
- Experience implementing analog layout designs to achieve tight matching, low noise, and low power consumption. Design components include CMOS, BJTs, resistors, capacitors, pad IOs, and ESD.
- Must recognize failure-prone circuit and layout structures, have experience with analog and DFM standard methodologies, and proactively work with the circuit design team to identify the best approach to solving problems.
- High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
- Technical understanding of IR drop, RC delay, electro-migration, self-heating, and coupling capacitance.
- Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.)
- Experience using Cadence Virtuoso's advanced features (XL, APR, and Constraint Manager)
- Programming/scripting knowledge in SKILL, Perl, TCL, Shell and/or Python
- Excellent communication skills and ability to work with multi-functional teams.
- Additional skill (plus): Cadence Innovus, CAD Automation experience, PCell creation experience, or familiar with Machine Learning and AI concepts
Education & Experience
Additional Requirements
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.