ASIC Timing Engineer

  • San Jose, CA
  • Posted 3 days ago | Updated 3 days ago

Overview

On Site
$65+
Contract - Independent
Contract - W2

Skills

Timing constraint development
Static Timing Analysis
Timing closure
Design collaboration RTL
Register Transfer Level
architecture
physical design
verification
Debugging and resolving timing issues
Performance optimization Performance
Power
Area
Clock domain crossing analysis
Multi-cycle and false path identification
Scripting and automation
Documentation and training
Floorplanning and physical implementation compatibility Synopsys PrimeTime
Cadence Encounter Timing System
ETS
TCL
Tool Command Language
Perl
Practical Extraction and Reporting Language
Python ASIC
Application-Specific Integrated Circuit
SDC
Synopsys Design Constraints
STA
PPA
Performance Power and Area
RTL
Tool Command Language ASIC
Python

Job Details

Job Title: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA - You must be already located in the San Jose area. 
Duration: 12+ Months
Visa: Open (No restrictions)

Responsibilities:

5 years of experience...

  • Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs

  • Perform static timing analysis (STA) to ensure full timing coverage and closure

  • Collaborate with RTL, architecture, and physical design teams on clock structures and design intent

  • Optimize constraints to meet performance, power, and area (PPA) goals

  • Debug timing issues: clock domain crossings, multi-cycle paths, and false paths

  • Write and maintain automation scripts using TCL, Perl, and Python

  • Document timing methodologies and train design teams on best practices

  • Ensure constraint compatibility with floorplanning, placement, and routing

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