Overview
On Site
$70 - $80
Part Time
Skills
mixed signal
verification
system verilog
analog
behavioral model
assertions
UVM
regression tests
DMS
DMS simulations
EEnet
Debug
Job Details
Job Title: Mixed Signal Verification Engineer
Location: Sunnyvale, California (Onsite)
Job Description -
We are looking for a Mixed Signal Verification Engineer with expertise in System Verilog real number modeling and a strong skill set in analog and digital simulations.
Key Responsibilities:
Proficient in System Verilog real number modeling
Writing regression tests and generating randomized vectors for analog behavioral model verification
Developing checkers and writing assertions
Hands-on experience with UVM
Expertise in gate-level parasitic annotated simulations
Strong debugging and communication skills
This role involves running mixed signal DMS simulations and developing System Verilog and EEnet-based analog models.
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